This question gets asked again and again, by beginners and experienced designers alike.
VHDL compared to Verilog
- A bit verbose, clunky syntax. I never liked that different constructs have different rules for the “end” tag, like “end synth” for architectures, versus “end component mux” for components. I always find myself looking up the syntax of packages and functions.
- Strongly typed: It’s a bit of a pain to have to make a (0 downto 0) vector to do something like a carry-in, but at the end of the day, it can save you time debugging problems. You don’t scratch your head as to why your 10-bit vector is only 0 to 1, because you assigned a 1-bit value to it (a thing you could do in Verilog, but in VHDL would produce a compile error). Also, by default Verilog undeclared signals default to 1-bit nets. Once I acciddentaly did this with a clock and I was wondering why nothing worked.
- Libraries: This is good and bad for me. It’s great to wrap your code in an organized and reusable manner. However, many “everyday” functions come from libraries rather than built into the language. There are non-standard libraries like std_logic_unsigned/std_logic_signed that are used in a lot of legacy code and old code examples. They’ve since been replaced by numeric_std. The conversion between types needs functions whose format is quite annoying.
- Writing code seems more streamlined. No component declarations, loose data types (everything is just bits, really).
- C-like syntax.
- Resulting code is more compact.
- Low-level descriptions are closer to actual hardware.
- Verilog has a poor design of its concurrency resolution scheme. Being an HDL, concurrency is obviously a very important aspect. Here is a write up concerning this point.
At the end of the day, the two languages are really able to achieve the same designs. I think it’s good to understand code in both languages, but since mixed language support is common, I don’t see an issue sticking with the one that you prefer.
To the comments from fft32, I would add that in my opinion, Verilog with its plain syntax is easier to learn and grasp for the beginner.
Also, from my experience, Verilog tends to be dominant in the ASIC arena, while VHDL is the language of choice for most FPGA designs.
?And the winner is
Well, none of the two, at least as these words are written. In the long run, as you advance in your HDL designer career, you will be probably using both, although also probably using one of them most of the time.
If you are wondering which one you should start with, take the one that you feel more comfortable with. Or, ask colleagues and teachers which one is most needed in the market niche you want to be part of. The important thing is to grasp the structures behind the language, and not the language itself.
To be honest, it seems that both fft32 and me mostly used VHDL, so this comparison could be a little biased. But, after all, both languages are Hardware Description Languages. So what really matters are the flip-flops and gates that give life to your design, and not so much how in what language you describe them.
Whatever you choose, good luck!
- It seems that Verilog got its syntax from C, and VHDL from Ada. I don’t know Ada so I couldn’t tell, but Verilog looks C’ish to me also.
- System Verilog is also a language worth checking, since it has powerful verification constructs.
- Many people talked about what seems to be the next step, which could leave VHDL and Verilog behind (as C left Assembler behind, might I add). The next step may well be High Level Synthesis. Altera, Xilinx and Chysel were mentioned as current HLS solution providers.
- Another HDL tool worth checking: MyHDL which reportedly uses the flexibility of Python for HDL editing
- And last, for the lighter side of the issue, some time ago there was a competition between VHDL and Verilog… For more details, check here (actually this is very old, and I don’t think its results are conclusive, but I thought I would be fun to mention it).