For me, and for many other designers, the first time we saw the internal memory blocks in an FPGA came as a little shock.
Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses (‘n’ has changed over the years, from plain DDR to current DDR4).
So, how comes that internal memories on an FPGA have TWO data buses? Isn’t that a waste of resources? Why don’t FPGAs have internal tri-state buses?
Well, until around fifteen years ago, some FPGA devices DID have internal tri-state buffers. With the evolution of semiconductors technology, internal tri-state buffers were abandoned. So today, FPGAs don’t have tri-state buffers but have unidirectional buses only. Since most memories are readable and writable, two unidirectional data buses are needed between a controller (CPU, internal FPGA logic) and the memory.
If this answer is enough for you, you can stop reading here. If you want to read some details about this absence of tri-state buffers on nowadays FPGAs, keep reading.
FPGAs are seas of resources (LUT, flipflops, RAM blocks, etc.) that have to be interconnected. When you describe a design using VHDL you are actually instructing the FPGA synthesizer how to fill those LUTs and how to connect between all the aforementioned blocks.
Until around 15 years ago, routing resources were much more abundant than logic blocks. So it was logic to include tri-state buffers. Buses built using tri-state buffers actually save design block resources by wasting more routing resources. But semiconductor technology kept advancing. At the device block level, the transistors are getting smaller (and faster).
On the other hand, as logic is reduced in size, routing resources actually get slower. A routing resource has width, height and length. As logic size is reduced, the mean length of the interconnections is also reduced. Since resistance is proportional to length but inversely proportional to the cross-section of the conductor, the total resistance of the interconnections get higher (so it is slower). Also, as conductors become closer, their mutual capacitance increases.
The influence of faster transistors and slower interconnections influences not only FPGAs but also all kinds of devices. One of the reasons for the appearance of multi-processors is that it is more efficient to use the faster transistors with shorter interconnection for each processor of the MP, instead of making a single complex device in the same die, where interconnections would severely limit transfer speed between the diverse sections of the device.
In summary, faster and more abundant transistors against slower interconnections have made that it is more efficient to dedicate many dedicated buses for data transfer between devices inside the FPGA (two unidirectional buses for each data connection), instead of the old ‘bus’ where all the devices hanged from the same data lines.
If the connections are between a central processor and several memories, the old data bus has been replaced by a star configuration (or hub).
If there are connections between several agents and devices, the old data bus will be replaced by a mesh network.
And no, there are not internal tri-state buses on an FPGA. Tri-state is only available at the I/O level, for connection with external memories.