Binary to seven segment decoder

The VHDL code presented below models a binary to seven segment decoder.

The decoder logic is a plain table, each ‘0’ in the output table corresponds to a bit lit on the seven segment display.

  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity bin2_7seg is
  6. port (
  7. data_in: in std_logic_vector (3 downto 0);
  8. data_out: out std_logic_vector (6 downto 0)
  9. );
  10. end bin2_7seg;
  11.  
  12. architecture rtl of bin2_7seg is
  13.  
  14. begin
  15. with data_in select data_out <=
  16. "1000000" when x"0",
  17. "1111001" when x"1",
  18. "0100100" when x"2", --
  19. "0110000" when x"3", -- ---0---
  20. "0011001" when x"4", -- | |
  21. "0010010" when x"5", -- 5 1
  22. "0000010" when x"6", -- | |
  23. "1111000" when x"7", -- ---6---
  24. "0000000" when x"8", -- | |
  25. "0011000" when x"9", -- 4 2
  26. "0001000" when x"a", -- | |
  27. "0000011" when x"b", -- ---3---
  28. "1000110" when x"c", --
  29. "0100001" when x"d",
  30. "0000110" when x"e",
  31. "0001110" when x"f",
  32. "1111111" when others;
  33. end rtl;

The VHDL code for this block is available at Github