For me, and for many other designers, the first time we saw the internal memory blocks in an FPGA came as a little shock. Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses ('n' has changed … Continue reading FPGA internal tri-state buses
Are you going to make an FPGA design? Are you asking yourself where to start, how to continue, and finish? These are the basic steps of an FPGA design flow: Design Requirements: A High Level Description of the desired functionality. Architecture Specification: In response to the Requirements, a High Level Design is produced. Normally this … Continue reading FPGA Design Flow Summary
An Entity defines the interface of a design unit. The elements of an entity are: Name of the entity Generic parameters Ports (connections of the entity) Most popular ports are of type in, out, and inout. The architecture specifies the behavior of an entity. An entity can be bonded to several architectures. Each architecture sees all the elements … Continue reading Component vs. Entity
VHDL is a strong typed language. It is also a language which has quite a long history. These two facts together make handling of signed and unsigned numbers quite confusing. Even today I see lots of code examples with incorrect treatment of signed and unsigned arithmetic. Part of the history of the VHDL language is … Continue reading Signed, unsigned and std_logic_vector
Men marry women wishing they will never change, but they do. Women marry men wishing they will be able to change them, but they don't. When I was young, even during my University studies, I was a real disaster in anything related to order. My room was always a mess. Whenever my mother or any … Continue reading Keeping your design files organized
This question gets asked again and again, by beginners and experienced designers alike. When I saw it posted on the FPGA group at reddit, I liked the answer from user fft32, so with his permission, I reproduce it here with some minor changes and additions. VHDL compared to Verilog VHDL: A bit verbose, clunky syntax. … Continue reading VHDL or Verilog?
Do you recognize that feeling when you think you knew something, until somebody asks you to explain it? Well, that was what happened to me when I tried to explain what "Analysis and Elaboration" is. I used it in Quartus many times, and I had a certain "knowledge" of what it was, but, what are … Continue reading Analysis and Elaboration