BeMicro CV – Introduction

The BeMicro CV is an Evaluation Board (EVB) based on Altera's Cyclone V FPGA. For a very low cost, this EVB offers the opportunity to evaluate and test our VHDL designs. On further entries of the blog, I will be including several projects based on this EVB. The BeMicro CV board features the following major … Continue reading BeMicro CV – Introduction


VHDL arbiter (III)

This is the third part of a series of articles on VHDL arbiters. On the first part, we commented what a VHDL arbiter is. On the second part, we saw the VHDL code for a fixed priority VHDL arbiter. When I talked about what a VHDL arbiter is, I gave the example of the single … Continue reading VHDL arbiter (III)

VHDL Arbiter – part II

In the previous installment, we defined what a HW arbiter is. Let's see a simple implementation of a VHDL arbiter. The arbiter has three inputs and three outputs. The logic is very simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests … Continue reading VHDL Arbiter – part II

Timers Block – Part Two

On the previous entry of this series we went through the VHDL source file and simulation of a Timer component. In this entry, we will instantiate several Timer components to create a timer bank (or block of timers). The code is attached below: The load_sel signal is an address bus that selects which timer to initialize. … Continue reading Timers Block – Part Two

Timers block

Hi. In this series of articles, we will experiment with the definition, implementation, simulation and synthesis of a block of timers in VHDL. Along the way, we will: Test the VHDL code blocks using Modelsim. Synthesize the VHDL code on Altera's Cyclone IV FPGA. NOTES: If you are asking yourself how to type in your VHDL … Continue reading Timers block