The demultiplexer receives one data bit din as input and routes it to one of ‘n’ possible outputs. The output is selected according the value of the sel input.
The demultiplexer size is configurable via a generic parameter SEL_W.
The decoder is simpler than the demultiplexer, there isn’t a din input. The sel input (of width w) is decoded into one output active (there are 2^w outputs). A demultiplexer can behave as a decoder if its data input is at constant value ‘1’.
The VHDL code for these blocks and testbench are available here.