Generic register with Load

The VHDL code presented below models a parallel register with load.

The register width is a generic parameter DATA_W.

  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity reg is
  5. generic (
  6. DATA_W : natural := 32
  7. );
  8. port (
  9. clk: in std_logic;
  10. rst: in std_logic;
  11.  
  12. -- inputs
  13. data_in: in std_logic_vector (DATA_W-1 downto 0);
  14. load: in std_logic;
  15.  
  16. -- outputs
  17. data_out: out std_logic_vector (DATA_W-1 downto 0)
  18. );
  19. end reg;
  20.  
  21. architecture rtl of reg is
  22.  
  23. begin
  24.  
  25. reg_pr: process (clk, rst)
  26. begin
  27. if (rst = '1') then
  28. data_out <= (others => '0');
  29. elsif (rising_edge(clk)) then
  30. if (load = '1') then
  31. data_out <= data_in;
  32. end if;
  33. end if;
  34. end process;
  35.  
  36. end rtl;

 

The VHDL code for this block and its testbench are available at Github.

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