This VHDL module receives parallel data from the data_in bus when load is asserted. One clock after load is de-asserted, the data is serially transmitted out on the data_out line, MSB first. The frame signal is asserted together with the end of the transmission (i.e. when the LSB is transmitted).
A busy signal informs the host on the parallel side that a transmission is ongoing.
The code uses the ieee.math library to calculate the width of the internal counter, based on the generic parameter that indicates the width of the parallel register (see line 34 of the architecture).
On the simulation, three ‘packets’ are sent. The cursors highlight the limit of the first sent packet, with value of 0xa, or 0b1010.
The VHDL code for this block and its testbench are available here.