This VHDL module receives serial data from the data_in line. The data is continuously shifted in. If a frame_in signal is detected, the data is latched in and the data_rdy output is asserted until the rd input is asserted by the host. The received data is available in parallel format on the data_out bus.
For the simulation, the Parallel to serial converter is used to generate data and the ser2par receives the data.
On the waveform below it can be seen the transmitted data and the received data by the ser2par module.
All the source files for this simulation can be found here.
- Add a ‘receiver ready’ line, as an output from the Serial to parallel converter. The Parallel to serial converter will sample this line and will start a new transmission only if this line is asserted. Modify both blocks and test them with a modified test-bench.
- Same as 1, but now the ‘receiver ready’ line serves as a flow control line. If the receiver de-asserts this line, the transmitter will keep (freeze) the last bit sent on the line, until the ‘receiver ready’ signal is asserted again. Check the modified blocks with a test-bench.