Cyclone V GX Starter kit – HW LED flasher

The first in the projects for the Cyclone V GX Starter kit will be a HW LED flasher. Although the design is very easy, it is a complete design including absolutely all the elements needed to achieve a reliable design with timing closure. For an introduction about the Cyclone V GX Starter kit evaluation board, … Continue reading Cyclone V GX Starter kit – HW LED flasher

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Functional Safety Primer for FPGA White Paper

by Bernard Murphy (*) Following up on their webinar on functional safety in FPGA-based designs, Synopsys have now published a white paper expanding on some of those topics. For those who didn’t get a chance to see the webinar this blog follows the white paper flow and is similar but not identical to my webinar … Continue reading Functional Safety Primer for FPGA White Paper

Cyclone V GX Starter Kit – Introduction

  The Cyclone V GX Starter kit is an Evaluation Board (EVB) from Terasic based on Altera's Cyclone V GX FPGA. The Cyclone V Starter Kit development board includes hardware such as Arduino Header, on-board USB Blaster, audio and video capabilities and much more On further entries of the blog, I will be including several … Continue reading Cyclone V GX Starter Kit – Introduction

Machine Learning Optimizes FPGA Timing

By Bernard Murphy (*) Machine learning (ML) is the hot new technology of our time so EDA development teams are eagerly searching for new ways to optimize various facets of design using ML to distill wisdom from the mountains of data generated in previous designs. Pre-ML, we had little interest in historical data and would … Continue reading Machine Learning Optimizes FPGA Timing

FPGA internal tri-state buses

For me, and for many other designers, the first time we saw the internal memory blocks in an FPGA came as a little shock. Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses ('n' has changed … Continue reading FPGA internal tri-state buses

SoC FPGA for IoT Edge Computing

One of the reasons for the explosive growth of IoT is that embedded devices with networking capabilities and sensor interfaces are cheap enough to deploy them at a plethora of locations. However, network bandwidth is limited. Not only that, but also, the latency of the network can be of seconds or minutes. By the time … Continue reading SoC FPGA for IoT Edge Computing

Timers Block – Part Three

On the previous entries of this series we already commented about: How to code a single timer block, and How to create a block of timers In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks. Memory blocks are an … Continue reading Timers Block – Part Three