Keeping your design files organized

Men marry women wishing they will never change, but they do. Women marry men wishing they will be able to change them, but they don't. When I was young, even during my University studies, I was a real disaster in anything related to order. My room was always a mess. Whenever my mother or any … Continue reading Keeping your design files organized

Timers block

Hi. In this series of articles, we will experiment with the definition, implementation, simulation and synthesis of a block of timers in VHDL. Along the way, we will: Test the VHDL code blocks using Modelsim. Synthesize the VHDL code on Altera's Cyclone IV FPGA. NOTES: If you are asking yourself how to type in your VHDL … Continue reading Timers block