VHDL editors – Notepad++

A good VHDL editor is terribly important during all the phases of your design cycle. Both Altera Quartus and Modelsim simulator include their own VHDL editors. Both tools include syntax highlighting. In the case of Altera Quartus editor, there is a very useful feature which is the possibility of entering templates for commonly used code … Continue reading VHDL editors – Notepad++


Timers block

Hi. In this series of articles, we will experiment with the definition, implementation, simulation and synthesis of a block of timers in VHDL. Along the way, we will: Test the VHDL code blocks using Modelsim. Synthesize the VHDL code on Altera's Cyclone IV FPGA. NOTES: If you are asking yourself how to type in your VHDL … Continue reading Timers block