Timers Block – Part Three

On the previous entries of this series we already commented about: How to code a single timer block, and How to create a block of timers In this third part of the series (as promised), we will show how to implement the timers block by using, not registers, but memory blocks. Memory blocks are an … Continue reading Timers Block – Part Three

Best FPGA development practices – Whitepaper

This whitepaper by Charles Fulk and RC Cofer is an excellent summary of several techniques, tools and design guidelines for FPGA: FPGA design process Revision control Coding guidelines Scripting automation PCB design for FPGA VHDL capture and simulation (including OS-VVM package) Project Management Design Resources The whitepaper is available here

Pseudo random generator Tutorial – Part 3

On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files. Chapter 5 - Matlab Formal Verification Our VHDL block implements an algorithm … Continue reading Pseudo random generator Tutorial – Part 3

Pseudo random generator Tutorial – Part 2

Modelsim Altera running an LFSR simulation On the first part of this tutorial, we started with a simple implementation of an LFSR block (Chapter 1) and it test bench (Chapter 2). Let's make our code a bit more professional. Chapter 3 - Upgrading the LFSR code Good code doesn't use hard-coded constants as were used … Continue reading Pseudo random generator Tutorial – Part 2

Pseudo random generator Tutorial

In this tutorial we will see how to design a block. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see: How to start with a simple block and gradually add features and improvements … Continue reading Pseudo random generator Tutorial

MIF_Gen – A Matlab Utility

Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target. One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means … Continue reading MIF_Gen – A Matlab Utility

VHDL editors – Notepad++

A good VHDL editor is terribly important during all the phases of your design cycle. Both Altera Quartus and Modelsim simulator include their own VHDL editors. Both tools include syntax highlighting. In the case of Altera Quartus editor, there is a very useful feature which is the possibility of entering templates for commonly used code … Continue reading VHDL editors – Notepad++