VHDL-2008 quick reference – COMPONENT declaration

COMPONENT declaration

component uart_tx is
  generic
  (
    SIM_MODE  : natural range 0 to 1 := 0  -- 1 for simulation, faster UART
  );
  port (
    reset_n   : in  std_logic;
    clk       : in  std_logic;
    tx_valid  : in  std_logic;
    tx_data   : in  std_logic_vector(UART_D_W-1 downto 0);
    tx_busy   : out std_logic;
    tx_out    : out std_logic
  );
end component uart_tx;

Note: The component declaration is to be included in the architecture declarative section (between the architecture statement and the begin statement that marks the start of the implementation description of the architecture)