VHDL-2008 quick reference – COMPONENT instantiation

COMPONENT instantiation

uart_tx_i : uart_tx 
  generic map
  (
    SIM_MODE  => 1
  )          
  port map (      
    reset_n   => rstn             , 
    clk       => clock_100        ,  
    tx_valid  => uart_tx_valid    ,
    tx_data   => uart_tx_data     ,
    tx_busy   => uart_tx_busy     ,
    tx_out    => uart_tx_out   
  );