Timers block


In this series of articles, we will experiment with the definition, implementation, simulation and synthesis of a block of timers in VHDL.

Along the way, we will:

  • Test the VHDL code blocks using Modelsim.
  • Synthesize the VHDL code on Altera’s Cyclone IV FPGA.


  1. If you are asking yourself how to type in your VHDL code, there are many options. Personally, I prefer Notepad++. But feel free to use your own tools. You can enter the code using Altera’s Quartus, Modelsim, or any other within a broad selection of tools available nowadays for free. Whichever tool you choose to use, the minimum requirements is that it supports VHDL, including syntax highlighting.
  2. This article has two parts. On the second part, a block of timers is instantiated.

First, let’s start with the code for a single timer block:



The first code block is the entity declaration. The timer block has, other than the standard clock and reset inputs:

  • A data_in bus and load signals to load the timer with an initial value.
  • An enable signal en to enable the timer down-counting

The width of the timer register is configurable via the generic parameter DATA_W.

Line 44 of the architecture takes care of the loading. If the timer reaches zero (line 48), the done signal is activated. The data_out bus is not strictly necesary for the functionality of the timer but was added for visibility during simulation.

To re-activate the timer after it reached zero, it must be loaded again.


All the examples in this site are according Altera recommended coding style. Altera recommends using asynchronous reset at the Flip Flop level.

Xilinx, on the other hand, recommends using synchronous reset at the FF level.

This important issue will be expanded in further entries of the blog.


Let’s have a look at the simulation. The first cursor marks the loading of the timer with the value ‘3’. Once enabled, the timer counts 3..2..1..0 and on the next clock the done signal is asserted.

Another cycle is shown following the second cursor marker. During this second timing cycle, the timer is momentarily disabled by de-asserting the en signal. It can be seen that the timer freezes at value six for one clock cycle, then resumes the countdown until done is asserted when the timer reaches the value zero.


You can download the source files for the timer block and its testbench by clicking on this link.

Go to the second article on the Timers’ Block series

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