Pseudo random generator Tutorial – Part 3

On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files. Chapter 5 - Matlab Formal Verification Our VHDL block implements an algorithm … Continue reading Pseudo random generator Tutorial – Part 3

Pseudo random generator Tutorial – Part 2

Modelsim Altera running an LFSR simulation On the first part of this tutorial, we started with a simple implementation of an LFSR block (Chapter 1) and it test bench (Chapter 2). Let's make our code a bit more professional. Chapter 3 - Upgrading the LFSR code Good code doesn't use hard-coded constants as were used … Continue reading Pseudo random generator Tutorial – Part 2

Pseudo random generator Tutorial

In this tutorial we will see how to design a block. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see: How to start with a simple block and gradually add features and improvements … Continue reading Pseudo random generator Tutorial

FPGA Design Flow Summary

Are you going to make an FPGA design? Are you asking yourself where to start, how to continue, and finish? These are the basic steps of an FPGA design flow: Design Requirements: A High Level Description of the desired functionality. Architecture Specification: In response to the Requirements, a High Level Design is produced. Normally this … Continue reading FPGA Design Flow Summary

VHDL editors – Notepad++

A good VHDL editor is terribly important during all the phases of your design cycle. Both Altera Quartus and Modelsim simulator include their own VHDL editors. Both tools include syntax highlighting. In the case of Altera Quartus editor, there is a very useful feature which is the possibility of entering templates for commonly used code … Continue reading VHDL editors – Notepad++

VHDL Arbiter – part II

In the previous installment, we defined what a HW arbiter is. Let's see a simple implementation of a VHDL arbiter. The arbiter has three inputs and three outputs. The logic is very simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests … Continue reading VHDL Arbiter – part II