Pseudo random generator Tutorial – Part 3

On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files. Chapter 5 - Matlab Formal Verification Our VHDL block implements an algorithm …

Pseudo random generator Tutorial – Part 2

Modelsim Altera running an LFSR simulation On the first part of this tutorial, we started with a simple implementation of an LFSR block (Chapter 1) and it test bench (Chapter 2). Let's make our code a bit more professional. Chapter 3 - Upgrading the LFSR code Good code doesn't use hard-coded constants as were used …

Pseudo random generator Tutorial

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FPGA Design Flow Summary

Are you going to make an FPGA design? Are you asking yourself where to start, how to continue, and finish? These are the basic steps of an FPGA design flow: Continue reading...

VHDL editors – Notepad++

A good VHDL editor is terribly important during all the phases of your design cycle. Both Altera Quartus and Modelsim simulator include their own VHDL editors. Both tools include syntax highlighting. In the case of Altera Quartus editor, there is a very useful feature which is the possibility of entering templates for commonly used code …

VHDL arbiter (III)

This is the third part of a series of articles on VHDL arbiters. In the first part, we commented on what a VHDL arbiter is. In the second part, we saw the VHDL code for a fixed-priority VHDL arbiter. When I talked about what a VHDL arbiter is, I gave the example of the single …

VHDL Arbiter – part II

In the first article of this series, we defined what an HW arbiter is. In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter. The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, …